Low Power Logic BIST with High Test Effectiveness

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概要

• 論文の詳細を見る

• Excessive test power has been a serious concern in BIST techniques. Shift power consumption can be significantly reduced by increasing the correlation among adjacent test data bits. However, this method may cause fault coverage loss. This paper presents a novel low power BIST scheme that reduces toggle probability of the scan input data while only shifting out part of capture responses for fault analysis and using the rest of capture responses as new test data. Using part of capture responses as test data can improve uniform distribution of 1s and 0s in test stimulus bits and thus result in high test effectiveness. Experimental results on larger benchmark circuits of ISCSAS89 and ITC99 show that the proposed strategy can reduce significantly test power while suppressing test coverage loss.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Xiang Lingyun

  College of computer and communication Engineering, Changsha University of Science and Technology

• Cai Shuo

  College of computer and communication Engineering, Changsha University of Science and Technology

• Wang Weizheng

  College of computer and communication Engineering, Changsha University of Science and Technology

• Liu Peng

  College of Information Science & Engineering, Hunan University

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• Low Power Logic BIST with High Test Effectiveness

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