A scan disabling-based BAST scheme for test cost reduction

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概要

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• This paper proposes a scan disabling-based BIST-aided scan test (BAST) scheme. In this scheme, a pseudo-random pattern generator(PRPG) generates test vector for each slice in multiple scan chains. Using scan disabling technique, the generated test vector is shifted into the scan chains until it is compatible with its corresponding slice for a deterministic test set with dont care bits. An automatic test equipment (ATE) only needs to store the control signals instead of test data. The proposed scheme that is based on the standard scan and uses any test set with dont care bits is widely applicable and easy to deploy. Its hardware overhead that is a PRPG, phase shifter, MISR and scan disable signal is very low. Theoretical analysis and experimental results show the proposed scheme can achieve higher compression gain compared with previous low cost scheme when care bits are few.

著者

• Wang Weizheng

  College of computer and communication Engineering, Changsha University of Science and Technology

• Liu Peng

  College of Information Science & Engineering, Hunan University

• Kuang Jishun

  College of Information Science & Engineering, Hunan University

• You Zhiqiang

  College of Information Science & Engineering, Hunan University

• Dou Zhiping

  China Academy of Machinery Science & Technology

• Dou Zhiping

  China Academy of Machinery Science & Technology

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