Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

概要

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To enable System-in-Package (SiP) solutions for analog products with active ICs or in combination with MEMS, passives or other components, a stacked Wafer-level Chip Scale Package (WCSP) platform has been developed using Through-Silicon Via (TSV) technology to create the smallest form factor package. This paper describes the integration flow and the development of the wafer over molding back-end unit process, using a 3 mm × 3 mm test vehicle on a 100 μm thick 200 mm wafer. Wafer-level over molding is a key development item as it provides support to the thin TSV wafers through the subsequent processes of debonding, ball attach and package singulation. Various molding materials and processes (compression, screen printing, film) were investigated. Selection of the mold material is a challenge as it must meet multiple requirements of processability, warpage, debondability, saw-singulation, and chip picking-up. Experimental results how to reduce warpage and Si damage by saw-singulation, and modeling results for the different mold materials and the pros/cons of the various molding processes are explained.
The Japan Institute of Electronics Packagingの論文