Architecture and Implementation of a Reduced EPIC Processor

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概要

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• This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13µm Nominal 1P8M process with 57M transistors. The die size of the REPICP is 100mm2 (10×10), and consumes only 12W power when running at 300MHz.

著者

• FENG Chaochao

  School of Computer, National University of Defense Technology

• ZHANG Minxuan

  School of Computer, National University of Defense Technology

• GAO Jun

  School of Computer, National University of Defense Technology

• XING Zuocheng

  School of Computer, National University of Defense Technology

関連論文

• A 1-Cycle 1.25GHz Bufferless Router for 3D Network-on-Chip
• A 1-Cycle 1.25GHz Bufferless Router for 3D Network-on-Chip
• Architecture and Implementation of a Reduced EPIC Processor

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