A 1-Cycle 1.25GHz Bufferless Router for 3D Network-on-Chip
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概要
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In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7×7 crossbar to achieve the frequency of 1.25GHz in TSMC 65nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.
著者
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Lu Zhonghai
Department Of Electronic Systems Royal Institute Of Technology
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FENG Chaochao
School of Computer, National University of Defense Technology
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ZHANG Minxuan
School of Computer, National University of Defense Technology
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Jantsch Axel
Department Of Electronic Systems Royal Institute Of Technology
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LU Zhonghai
Department of Electronic Systems, Royal Institute of Technology
関連論文
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