An all-digital PLL with supply insensitive digitally controlled oscillator

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概要

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• This paper presents a divider-less all-digital PLL (ADPLL) with supply insensitivity. We employ a feed-forward inverter to make the oscillator insensitive to supply variation and utilize the delta-sigma modulation to improve the resolution. The on-chip calibration tracks the optimum compensation strength for process and nominal voltage variations. We use an asynchronous counter to decide the phase error for low power. The proposed ADPLL was fabricated in a 0.13µm CMOS process. The silicon area of the ADPLL is 0.26mm2 and the power consumption is 5.8mW at 320MHz. The spur level with the proposed compensation scheme was improved from −57dBc to −84dBc with an intentional supply noise.

著者

• Jun Young-hyun

  Memory Division Samsung Electronics Corporation

• Seo Seong-Young

  College of Information and Communication Engineering, Sungkyunkwan Univesity

• Chun Jung-Hoon

  College of Information and Communication Engineering, Sungkyunkwan Univesity

• Kwon Kee-Won

  College of Information and Communication Engineering, Sungkyunkwan Univesity

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• An all-digital PLL with supply insensitive digitally controlled oscillator

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