High-speed modulo (2<I><SUP>n</SUP></I>+3) multipliers
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概要
- 論文の詳細を見る
In this express, we propose an improved architecture for modulo (2<I><SUP>n</SUP></I>+3) multiplication on the condition n≥6. With this architecture, we can design the fastest among all known modulo (2<I><SUP>n</SUP></I>+3) multipliers. The proposed modulo (2<I><SUP>n</SUP></I>+3) multiplier can improve the state-of-art by 3.2% on the average in terms of area and 10.1% on the average in terms of performance delay.
著者
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Li Lei
Research Institute Of Electronic Science And Technology University Of Electronic Science And Technology Of China
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Zhou Wanting
Research Institute Of Electronic Science And Technology University Of Electronic Science And Technology Of China
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Zhou Lu
Research Institute of Electronic Science and Technology, University of Electronic Science and Technology of China
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