Cooperative communication based barrier synchronization in on-chip mesh architectures

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概要

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• We propose cooperative communication as a means to enable efficient and scalable barrier synchronization on mesh-based many-core architectures. Our approach is different from but orthogonal to conventional algorithm-based optimizations. It relies on collaborating routers to provide efficient gather and multicast communication. In conjunction with a master-slave algorithm, it exploits the mesh regularity to achieve efficiency. The gather and multicast functions have been implemented in our router. Synthesis results suggest marginal area overhead. With synthetic and benchmark experiments, we show that our approach significantly reduces synchronization completion time and increases speedup.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• CHEN Shuming

  National University of Defense Technology

• Liu Hai

  National University of Defense Technology

• Chen Xiaowen

  National University of Defense Technology

• Lu Zhonghai

  KTH - Royal Institute of Technology

• Jantsch Axel

  KTH - Royal Institute of Technology

関連論文

• Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures
• Cooperative communication based barrier synchronization in on-chip mesh architectures

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