A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18µm CMOS

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概要

• 論文の詳細を見る

• In this paper a fully differential comparator-based switched-capacitor (CBSC) pipelined ADC is presented. For better performance and accuracy, we modified the differential architecture and introduced some practical issues on preset levels designing. For comparison, we used a simple comparator which can compensate offset easily. Finally we designed a 12b 40MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 75.2-dB spurious-free-dynamic range (SFDR) and 69.78-dB SNDR. In addition it consumes 4.1mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 460fJ/step.

著者

• Zamani Majid

  Department of Electrical Engineering, science and research Branch of Islamic Azad University

• Jafarabadi-Ashtiani Shahin

  School of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran

• Dousti Masoud

  Department of Electrical Engineering, science and research Branch of Islamic Azad University

• Naser-Moghadasi Mohammad

  Department of Electrical Engineering, science and research Branch of Islamic Azad University

関連論文

• A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18µm CMOS
• A10b, 20-MS/s, 2.6mW fully differential CBSC pipelined ADC in 0.18µm CMOS

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