Design of Asynchronous Multi-Bit OTP Memory

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概要

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• We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5V) and an external program voltage VPPE (=8.5V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128bytes is designed with Magnachip 0.13µm CMOS process. The layout area is 229.52× 495.78µm2.

著者

• CHOI Chul-Ho

  Department of Computer Engineering, Kyungpook National University

• LEE Jae-Hyung

  Department of Electronic Engineering, Changwon National University

• KIM Tae-Hoon

  Department of Electronic Engineering, Changwon National University

• SHIM Oe-Yong

  Department of Electronic Engineering, Changwon National University

• HWANG Yoon-Geum

  Department of Electronic Engineering, Changwon National University

• AHN Kwang-Seon

  Department of Computer Engineering, Kyungpook National University

• HA Pan-Bong

  Department of Electronic Engineering, Changwon National University

• KIM Young-Hee

  Department of Electronic Engineering, Changwon National University

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