An improved reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1}

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概要

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• In this paper, a new reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1} is presented. We improved a previously introduced reverse converter architecture for deriving a high-speed hardware design. Hardware architecture of the proposed converter is based on adders, without the need for ROM or Multiplier. The presented design resulted in a significant reduction in conversion delay in comparison to the last reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1}.

著者

• Navi Keivan

  Department Of Electrical And Computer Engineering Shahid Beheshti University

• Navi Keivan

  Department of Electrical and Computer Engineering, Shahid Beheshti University

• Hosseinzadeh Mehdi

  Ph.D Student, Science & Research Branch, Islamic Azad University (IAU)

• Molahosseini Amir

  Ph.D Student, Science & Research Branch, Islamic Azad University (IAU)

関連論文

• Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2^,2^n-1,2^-1} and {2^,2^n-1,2^-1}
• An improved reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1}
• A new five-moduli set for efficient hardware implementation of the reverse converter

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