Effects of Wafer Cleaning on the Interconnect Structure and Its Electrical Properties during the Al Dual Damascene Process for the Fabrication of Sub-100nm Memory Devices

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概要

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• An Al dual damascene process for the metallization of sub-100 nm dynamic random access memory devices was performed, and the effects of wafer cleaning method on the damascene structures and their electrical properties were investigated. Interconnect structures obtained with the Al dual damascene process using the conventional NH4OH-based wet cleaning (Type I) and the wet cleaning followed by CF4/Ar-plasma dry cleaning (Type II) showed that the metal lines having the aspect ratio of 3 were patterned without gap-filling of inter metal dielectrics. All the sheet resistances of metal lines using the two different wafer cleaning methods during the Al dual damascene process were within specification. The via resistance distributions, however, depended on the cleaning method, and it was found that the cleaning Type II produced a 100% yield and very narrow distribution of the contact resistances of the 0.24 μm-diameter via due to the efficient removal of stable AlxOy species for cleaning Type II.

• 社団法人 化学工学会の論文
• 2005-11-01

著者

• Ryu Hyun-kyu

  Corporate Research And Development Lg Chem Ltd.

• Shin Chee

  Department Of Chemical Engineering Ajou University

• KIM Yil-Wook

  Memory Research and Development Division, Hynix Semiconductor Inc.

• KIM Chang-Koo

  Department of Chemical Engineering, Ajou University

• Kim Chang-koo

  Department Of Chemical Engineering Ajou University

• Kim Yil-wook

  Memory Research And Development Division Hynix Semiconductor Inc.

関連論文

• Effects of Wafer Cleaning on the Interconnect Structure and Its Electrical Properties during the Al Dual Damascene Process for the Fabrication of Sub-100nm Memory Devices

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