A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition

スポンサーリンク

概要

• 論文の詳細を見る

• Since many embedded applications involve intensive mathematic operations floating-point arithmetic units (FPU) have paramount importance in embedded systems. However previous implementations of FPU either require much manual work or only support special functions (e.g. reciprocal square root logarithm etc.). In this paper we present an automatic method to synthesize general FPU by aligned partition. Based on the novel partition algorithm and the concept of grouping floating-point numbers into zones our method supports general functions of wide irreducible domain. The synthesized FPU achieves smaller area higher frequency and greater accuracy. Experimental results show that our method achieves 1) on average 90% smaller and 50% faster indexer than the conventional automatic method; 2) on the hyperbolic functions 20 k times smaller error rate and 50% use of LUTs and flip-flops than the conventional manual design.

• 一般社団法人情報処理学会の論文
• 2008-08-27

著者

• GE Liangwei

  Graduate School of IPS, Waseda University

• Song Chen

  Graduate School of Information Production and System Waseda University

• Liangwei Ge

  Graduate School of Information Production and System Waseda University

• Yuichi Nakamura

  NEC Central Research Lab.

• Takeshi Yoshimura

  Graduate School of Information Production and System Waseda University

関連論文

• Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs
• Max-Flow Scheduling in High-Level Synthesis(VLSI Design Technology and CAD)
• Post-Scheduling Frequency Assignment for Low Power High-Level Synthesis
• A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition
• Exploration of Schedule Space by Random Walk
• A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools

スポンサーリンク