Hardware Efficient Hybrid Logarithmic Approach For RRC filter Design in DVB-S2 Receiver

概要

論文の詳細を見る
Computational complexity of a Root Raised Cosine Filter is dominated by the binary multiplications involved in process. In this paper, a hybrid logarithmic approach has been used to design multiplier-less RRC filter to achieve optimized hardware. Hybrid-logarithmic arithmetic is advantageous for FIR digital filters since it removes the necessity for the use of high speed array multipliers. These are replaced by simple look up tables for the conversion to and from the logarithmic domain. Matlab simulations have been performed to show the performance of hybrid-logarithmic filter. It offers a significant reduction in complexity when compared to floating point equivalents proposed for the DVB-S2 receiver applications. The use of hybrid logarithmic arithmetic also has the potential to reduce the power consumption, latency and hardware complexity. The given approach can be used with other DVB-S2 receiver techniques like symbol timing synchronization, carrier offset estimation etc. It can be used in high speed communication of DVB-S2 because of its simplified architecture. The proposed design shows a huge amount of hardware saving over the conventional binary multiplier approach. The functionality of the design has been verified through simulation and synthesis of the existing and proposed RRC filter scheme.
2010-10-21