A target impedance of power distribution network and LSI packaging design (集積回路)

概要

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This paper describes the modeling analysis for a power distribution network and demonstrate co-design and co-simulation in using the detailed prototype model, which includes chip, package and printed circuit board. A circuit simulator and a 2D solver using the finite element method are used to study the frequency and transient responses for the core switching noise. In the model, we assume a chip model (current profile and on-chip capacitance) and define the circuit parameters with an equivalent circuit to meet the target impedance. Then the physical design of the package and printed circuit board were examined to get all of the required circuit parameters. According to the modeling and evaluation, the package design with both the low equivalent series inductance capacitors and the low equivalent series resistance capacitors in the bottom layer with a thin core structure is more advantageous than a capacitor in the top layer.
社団法人電子情報通信学会の論文
2009-11-25