C-016 Design and Architecture of Queue Processor Computing Among queue Words and Random Access Registers (QRP)

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概要

• 論文の詳細を見る

• In this paper we propose Queue with Register Processor (QRP) architecture that can compute among Queue words and random access registers. QRP consists queue registers as well as random access registers for its storage. First we introduce QRP computing model then we introduce hardware structure for proposed model. Each unit of QRP hardware behavior model was tested for its functionality using VerilogHDL. Evaluating process is still continuing for proposed architecture.

• FIT(電子情報通信学会・情報処理学会)推進委員会の論文
• 2005-08-22

著者

• Sowa Masahiro

  電通大

• Dinesh Dahanayakage

  電通大

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