Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm(VLSI Systems)
スポンサーリンク
概要
- 論文の詳細を見る
If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.
- 2006-07-01
著者
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ICHIKAWA Shuichi
Department of Knowledge-based Information Engineering, Toyohashi University of Technology
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ATONO Ryoichiro
Department of Knowledge-based Information Engineering, Toyohashi University of Technology
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Ichikawa Shuichi
Department Of Internal Medicine Cardiovascular Hospital Of Central Japan (kitakanto Cardiovascular H
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Atono Ryoichiro
Department Of Knowledge-based Information Engineering Toyohashi University Of Technology:(present Of
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Ichikawa Shuichi
Department Of Knowledge-based Information Engineering Toyohashi University Of Technology:intelligent
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Ichikawa Shuichi
Department Of Internal Medicine Cardiovascular Hospital Of Central Japan
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