Diversification of Processors Based on Redundancy in Instruction Set
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概要
- 論文の詳細を見る
By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.
- 2008-01-01
著者
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ICHIKAWA Shuichi
Department of Knowledge-based Information Engineering, Toyohashi University of Technology
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SAWADA Takashi
Department of Knowledge-based Information Engineering, Toyohashi University of Technology
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HATA Hisashi
Department of Knowledge-based Information Engineering, Toyohashi University of Technology
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Ichikawa Shuichi
Department Of Internal Medicine Cardiovascular Hospital Of Central Japan (kitakanto Cardiovascular H
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Sawada Takashi
Department Of Knowledge-based Information Engineering Toyohashi University Of Technology
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Hata Hisashi
Department Of Knowledge-based Information Engineering Toyohashi University Of Technology
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Ichikawa Shuichi
Department Of Internal Medicine Cardiovascular Hospital Of Central Japan
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Sawada Takashi
Department of Chemistry, Nagaoka University of Technology, Nagaoka 940-2188, Japan
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