Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications(Electronic Circuits)

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概要

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• A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when V_<DDL>/V_<DDH>=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.

• 2007-07-01

著者

• Min Kyeong-sik

  School Of Electrical Engineering Kookmin University

• Min Kyeong-sik

  School Of Electrical Engineering Kook-min University

• KWON O-Sam

  School of Electrical Engineering, Kookmin University

• Kwon O-sam

  School Of Electrical Engineering Kookmin University

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