Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

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概要

• 論文の詳細を見る

• In this paper, we propose the sub-block Active-Mode Power Gating (AMPG) scheme to reduce the active-mode leakage and apply it to the 32-bit Carry Select Adder (CSA), where the sub-blocks are activated and deactivated according to the idleness during the active time. By doing so, we can reduce the active-mode energy by 21% at the cycle time of 10ns for the 22-nm node compared to the conventional AMPG. The critical path delay is degraded as little as 1% in the sub-block AMPG. For a given power budget as small as 100µW, the new sub-block AMPG with 32-nm node can run faster by 47% than the conventional AMPG.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Min Kyeong-sik

  School Of Electrical Engineering Kook-min University

• Vo Huan

  School of Electrical Engineering, Kookmin University

• Jung Chul-Moon

  School of Electrical Engineering, Kookmin University

• Lee Eun-Sub

  School of Electrical Engineering, Kookmin University

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• Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

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