A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost(Circuit Synthesis,<Special Section>VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• Because the leakage current of a digital circuit depends on the states of the circuit's logic gates, assigning a minimum leakage vector (MLV) for the primary inputs and the flip-flops' outputs of the circuit that operates in the sleep mode is a popular technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn vector controller, our technique can take this overhead into account. Ignoring this overhead during solution space exploration may bring a side effect that is misrecognizing a non-optimal solution as an optimal one. Experimental results show that our heuristic algorithm can reduce the leakage current up to 59.5% and can find the optimal solutions on most of the small MCNC benchmark circuits. Moreover, the required CPU time of our probability-based program is significantly less than that of a random search program.

• 社団法人電子情報通信学会の論文
• 2007-12-01

著者

• WU Tsung-Yi

  National Changhua University of Education

• Wu Tsung‐yi

  National Changhua Univ. Education Twn

• Tzeng Jr-luen

  National Changhua University Of Education

関連論文

• Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
• A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates

スポンサーリンク