Low-Leakage and Low-Power Implementation of High-Speed Logic Gates

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, our proposed 65nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.

• （社）電子情報通信学会の論文
• 2009-04-01

著者

• Lu Liang-ying

  National Changhua University Of Education

• WU Tsung-Yi

  National Changhua University of Education

関連論文

• Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
• A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates

スポンサーリンク