Instruction Based Synthesizable Testbench Architecture(Integrated Electronics)

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概要

• 論文の詳細を見る

• This paper presents a synthesizable testbench architecture based on a defined instruction for standalone mode verification. A set of instructions describes transitions of a signal. The set of instructions can be changed easily to describe different signal transitions by loading the different set of instructions on emulator's memory. The proposed testbench enables a fast emulation and increases flexibility and reusability by using an instruction set. To prove the performance of instruction based synthesizable testbench, we verified Bluetooth and IEEE802.11a PHY baseband systems and compared their performance with those of co-sim mode and modified co-sim mode emulation.

• 社団法人電子情報通信学会の論文
• 2006-05-01

著者

• Park Sin-chong

  Bit Engineering Laboratory Pertains To System Integration Technology Institute (siti) Information An

• Park Sin-chong

  Bit Engineering Laboratory Pertaining To System Integration Technology Institute (siti) Information

• Choi Ho-seok

  Bit Engineering Laboratory Pertains To System Integration Technology Institute (siti) Information An

• CHOI Hae-Wook

  Bit Engineering Laboratory pertaining to System Integration Technology Institute (SITI), Information

• Choi Hae-wook

  Bit Engineering Laboratory Pertaining To System Integration Technology Institute (siti) Information

関連論文

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• MIMO Detector Based on Trellis Structure
• Low Latency and Memory Efficient Viterbi Decoder Using Modified State-Mapping Method(Fundamental Theories for Communications)
• Instruction Based Synthesizable Testbench Architecture(Integrated Electronics)

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