A 10b 100MS/s 1.4mm^2 56mW 0.18μm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors(Electronic Circuits)
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概要
- 論文の詳細を見る
This work proposes a 10b 100MS/s 1.4mm^2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18μm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7dB, an SFDR of 61.5dB, and the power dissipation of 56mW at 100MS/s.
- 社団法人電子情報通信学会の論文
- 2006-05-01
著者
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Lee Seung-Hoon
Dept. of Electronic Engineering, Sogang University
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Lee Seung-hoon
Dept. Of Electronic Engineering And Interdisciplinary Program Of Integrated Biotechnology Sogang Uni
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Cho Young‐jae
Sogang Univ. Seoul Kor
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MIN Byoung-Han
Dept. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang Un
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CHO Young-Jae
Dept. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang Un
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CHAE Hee-Sung
Dept. of Electronic Engineering and Interdisciplinary Program of Integrated Biotechnology, Sogang Un
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PARK Hee-Won
LG Electronics Company
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Cho Young-jae
Dept. Of Electronic Engineering And Interdisciplinary Program Of Integrated Biotechnology Sogang Uni
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Chae Hee-sung
Dept. Of Electronic Engineering And Interdisciplinary Program Of Integrated Biotechnology Sogang Uni
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Min Byoung-han
Dept. Of Electronic Engineering And Interdisciplinary Program Of Integrated Biotechnology Sogang Uni
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