An 8b 52MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications

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概要

• 論文の詳細を見る

• This paper describes an 8b 52MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8μm CMOS process shows nonlinearities less than ±0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52MHz sampling rate with 230mW.

• 社団法人電子情報通信学会の論文
• 2001-04-01

著者

• Moon J‐w

  Sogang Univ. Seoul Kor

• Lee Seung-hoon

  Dept. Of Electronic Engineering And Interdisciplinary Program Of Integrated Biotechnology Sogang Uni

• Lee Sung-ho

  Made Technology Co.

• MOON Jung-Woong

  Dept. of Electronic Engineering, Sogang University

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• An 8b 52MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications

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