Scaling Parameter Dependent Drain Induced Barrier Lowering Effect in Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor field Effect Transistor

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概要

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• A simple model equation to study the effect of drain induced barrier lowering (DIBL) parameters on device performance for a double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is proposed. This model equation is used to study the influence of various device parameters on the DIBL effect. The main conclusions drawn from the present study are that: (1) two different approaches for determining the DIBL parameter lead to the same model equation and (2) it is easier to calculate the DIBL parameter rather than extract it from the I-V plots. This model is also easy to implement in a circuit simulator. It is found that the DIBL parameter is almost inversely proportional to the channel length and directly proportional to the gate oxide and silicon thickness. It is shown that a DIBL parameter of less than 0.1 down to a gate length of 0.1 μm is possible at lower Si thicknesses.

• 社団法人応用物理学会の論文
• 1999-04-01

著者

• Samudra Ganesh

  Department Of Electrical And Computer Engineering National University Of Singapore

• RAJENDRAN Krishnasamy

  Department of Electrical Engineering, Faculty of Engineering, National University of Singapore

• SAMUDRA Ganesh

  Department of Electrical Engineering, Faculty of Engineering, National University of Singapore

関連論文

• Theoretical Analyses of Oxide-Bypassed Superjunction Power Metal Oxide Semiconductor Field Effect Transistor Devices
• Shape Effects on the Performance of Si and Ge Nanowire Field-Effect Transistors Based on Size Dependent Bandstructure
• Scaling Parameter Dependent Drain Induced Barrier Lowering Effect in Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor field Effect Transistor

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