Electrical Properties of Platinum-Silicon Contact Anneled in an H_2 Ambient

概要

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Annealed platinum-silicon contact electrical properties have been consistently investigated at the range of 6.0×10^<15>〜8.5×10^<19>cm^<-3> silicon carrier consentration N_D and in the 200〜700℃ annealing temperture range. For diodes heat-treated at 300℃, having N_D=6×10^<15>cm^<-3>, nearly ideal Schottky barrier diodes are obtained. For N_D >__-7×10^<18>cm^-3, ohmic contact is obtained. The situation is almost unchanged for up to the 500℃ annealing temperature. However, by heat-treatment at above 600℃, the effective barrier height rapidly decreases and the carrier concentration range. Which yield ohmic contact characteristics, moves to lower values. These phenomena are satisfactorily interpreted on terms of "impurity pile up effect. "The impuritise pile-up is revealed by the Auger electron spectroscopy analysis. Arsenic impurities are piled up at the platinum silicide-silikon interface. Presumably, piled up impurities near PtSi-Si interface are electrically activated at above the 600℃ annealing temperture. Effectively, the interface carrier concentration is increased by about one order of magnitude in regard to the silicon substrate carrier consentration by 600℃ annealing.
社団法人応用物理学会の論文
1978-06-05