Bottom Electrode Structures of Pt/Ru Deposited on Polycrystalline Silicon for Semiconductor Memory Capacitors

概要

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The ruthenium buffer layers for platinum deposition onto polycrystalline silicon (poly-Si) were formed by dc sputtering and metalorganic chemical vapor deposition (MOCVD) for high dielectric constant (Ba,Sr)TiO_3 (BST) capacitor integration. The electrode structures of Pt/dc-sputtered Ru/poly-Si annealed for 1h at 700℃ in oxygen ambient (760 Torr) showed severe intermixing between Pt and Ru and showed greatly rough morphologies by the RuO_x phases formed on platinum surface during annealing in O_2. On the other hand, those of Pt/MOCVD-Ru/poly-Si annealed at 700℃ showed smooth surface microstructure without any second phases on platinum. Contacts in the annealed Pi/dc-sputtered Ru/poly-Si and Pt/MOCVD-Ru/poly-Su structures showed a specific contact resistance of 4.0×10^<-2> and 1.5×10^<-5> Ω・cm, respectively. In Pt/BST/Pt/Ru/poly-Si capacitor structure formed at 500℃, leakage current characteristics and dielectric properties measured between top Pt and bottom Pt showed almost similar values to those measured between top Pt and poly-Si. The bottom electrode structures of Pt/Ru/poly-Si formed by MOCVD are greatly attractive for high density memory BST capacitor integration.
社団法人電子情報通信学会の論文
1999-07-23