ED2000-54 / SDM2000-54 Microprocessor Technologies beyond GHz
スポンサーリンク
概要
- 論文の詳細を見る
Aggressive transistor scaling has been the key factor for high performance microprocessor fabrication. As a result, the gate oxide is now in a regime that large direct tunneling leakage current might cause a serious circuit instability, reliability problem and high power consumption. Ultra-shallow S / D extension is also a limiting factor in terms of the trade-off between short-channel effect suppression and high series resistance. The threshold voltage scaling limit due to the signal-to-noise margin makes hard to meet the transistor performance target for low power supply voltage. SOI device provides an attractive solution in terms of low voltage / power operation and improved performance. However, its inherent floating body effects must be carefully engineered for the successful circuit integration. Pass-gate leakage current and history-dependent switching delay are the most important issues to be addressed. Future sub-0.13μm generation will requir SOI device architecture with new gate dielectric, elevated S / D extension and metal gate electrode. Interconnect delay is another significant factor in chip performance. Future interconnect technology will require a new material such as Cu with low resistivity and high electromigration resistance, as well as low-k intermetal dielectrics (MD) with reliable thermal and electrical properties.
- 社団法人電子情報通信学会の論文
- 2000-06-21
著者
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Ahn J‐h
Samsung Electronics Co. Ltd.
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Suh Kwang-pyuk
Samsung Electronics Co. Ltd.
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Lee S‐c
Hyundai Electronics Ind. Co. Ltd. Kyoungki‐do Kor
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Lee Soo-cheol
Samsung Electronics Co. Ltd.
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Ahn Jong-hyun
Samsung Electronics Co. Ltd.
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Yang Jeong-hwan
Samsung Electronics Co. Ltd.
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Kim Young-wug
Samsung Electronics Co. Ltd.
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Park Sung-Pae
Samsung Electronics Co., Ltd.
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Park Sung-pae
Samsung Electronics Co. Ltd.
関連論文
- ED2000-54 / SDM2000-54 Microprocessor Technologies beyond GHz
- ED2000-54 / SDM2000-54 Microprocessor Technologies beyond GHz
- Device Performance Improvement Based on Transient Enhanced Diffusion Suppression in the Deep Sub-Quarter Micron Scale
- Device Performances Improvement Based on TED Suppression in Deep Sub-Quarter Micron Regime