Gate Oxide Degradation during Polysilicon Etching in a Parallel Plate Plasma Type Etcher

概要

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Gate oxide degradation by transient surge current has been tested during polysilicon etching in a parallel plate plasma type etcher. To reduce the transient surge current, rf power is removed gradually at a rate of 50W/sec after 50% overetch. Breakdown voltage distribution measured at MOS capacitor array structure with gates is improved considerably by the ramping down of rf power. This clearly indicates that the transient surge current can cause charge damage to some extent even in a plasma type etcher. Gate oxide recovery during the inter-poly oxide deposition is also discussed.
社団法人電子情報通信学会の論文
1995-07-28