V_<GS>-V_<TH> Scaling for Low Power CMOS Circuit

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概要

• 論文の詳細を見る

• A simple formula is proposed for the analysis of gate delay of CMOS gate in the low V_<GS>-V_<TH> scaling. The effects of device parameters on gate delay can be readily found so that the formula can be used to design the device parameters in the low V_<DD> CMOS circuit. The measured results confirm the utilization of the proposed formula and quantifies the importance of V_<TH> effects under low voltage operation.

• 社団法人電子情報通信学会の論文
• 1995-07-28

著者

• Park Young-june

  Dept. Of Electronics Eng. And Inter-university Semiconductor Research Center Seoul National Universi

• Kang Dae-gwan

  Dept. Of Electronics Eng. And Inter-university Semiconductor Research Center Seoul National Universi

• Min Hong-Shick

  Dept. of Electronics Eng. and Inter-University Semiconductor Research Center Seoul National Universi

• Min Hong-shick

  Dept. Of Electronics Eng. And Inter-university Semiconductor Research Center Seoul National Universi

関連論文

• V_-V_ Scaling for Low Power CMOS Circuit
• Improvement of Breakdown Voltage in SOI MOSFET Using Gate-Recess (GR) Structure

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