Concurrent Error Detection for Asynchronous Circuits using Current Sensing Techniques
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概要
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Concurrent error detection (CED) in clocked electronic systems is achieved by encoding the inputs and the outputs using error detecting codes and organizing the circuit such that the fault is propagated to the primary outputs as the first non-codeword output, immediately after its occurrence. The error indication is obtained by monitoring the logic levels at the primary outputs using a checker circuit. On the other hand, concurrent error detection in asynchronous / self-timed circuits pose different kind of problems. In spite of encoding the inputs and the outputs with error detecting codes and proper organization of the circuit, occurrence of permanent logical faults in self-timed combinational circuits may manifest as undetectable timing errors at the outputs. Design of reliable asynchronous circuits is an important issue in view of fast growing application of asynchronous systems. In this paper we consider the problem of concurrent error detection in quasi-delay-insensitive (QDI) circuits, which are a subclass of self-timed circuits. QDI combinational circuits are designed based on the assumption that stray delays of all the decision elements as well as the interconnects of the circuit are finite but unbounded, with the weakest compromise known as isochronic fork assumption. Due to unbounded delay assumption, QDI circuits process the information based on a request-acknowledge hand-shake protocol. Thatis, the external environment applies fresh inputs to the QDI circuit only after it receives a completion signal from the circuit indicating that the previous inputs have been processedand the circuit is stable. Isochronic-fork assumption implies that, when a transition on one output of the forking wire is acknowledged, and thus completed, the transition on all outputs of the forking wires are acknowledged and thus completed. Suchan assumption stipulates that the delays of all forking wiresare the same, or at least difference in the delays of forking wires is smaller than the delay of an elementary decision element.
- 一般社団法人電子情報通信学会の論文
- 1996-03-11
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関連論文
- 「WCC98に参加して/IFIP TC : この1年」
- Concurrent Error Detection for Asynchronous Circuits using Current Sensing Techniques