Cone/Block Methods for Logic Simulation Time Reduction in E-Beam Guided-Probe Diagnosis (Special Issue on LSI Failure Analysis)

概要

論文の詳細を見る
Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation data also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110 k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.
社団法人電子情報通信学会の論文
1994-04-25