Design and Evaluation of the MULHI Cache

概要

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Instruction caches, which offer large bandwidth and high hit ratio, are indispensable for VLIW processors. We have proposed an instruction cache mechanism, named MULHI (MULtible HIt) cache, in order to make the instruction fetch and issue faster. Our previous study showed that the MULHI cache significantly reduces the execution cycles in standard benchmark programs. However, the MULHI cache needs more complex control logic than conventional ones, such as the NOP cache, so that it may increase the critical path length and result in the slower operation of the instruction pipeline. To examine the performance of the MULHI cache in consideration of hardware complexity, we practically designed it using a 0.5-μm CMOS technology. The evaluation results of the hardware design show that the control logic does not affect the critical path of the instruction pipeline. In addition, the simulation results using the SPEC95 benchmark suite show that the MULHI cache outperforms than the SILO cache, which has been proposed as a high-performance instruction cache for VLIW processors.
社団法人電子情報通信学会の論文
2002-03-01