A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks (Special Section of Letters Selected from the '92 Fall Conference and the '93 Spring Conference)

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概要

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• This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The N×N matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N^2 to (N / D)^2. Each block contains N / D input lines and N / D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N / D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of ^<-8> is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit / s high-speed ATM swtch fabric needed for B-ISDN.

• 社団法人電子情報通信学会の論文
• 1993-07-25

著者

• Endo Ken-ichi

  Ntt Communication Switching Laboratories

• YAMANAKA Naoaki

  NTT Communication Switching Laboratories

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• A High-Speed ATM Switch that Uses a Simple Retry Algorithm and Small Input Buffers (Special Section of Letters Selected from the '92 Fall Conference and the '93 Spring Conference)
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