Register-Transfer Level Testability Analysis and Its Application to Design for Testability (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• In this paper, we propose a new register transfer level (RT level) testability analysis method. Controllability and obsrvability measures are defined for signal vectors based on the numbers of values they can take. The control part and the datapath part are automatically identified in the given RT level model and distinctive analysis methods are applied. We also describe a DFT point selection method based on our testability measures. In a experiment on a signal processing circuit whose gate count is 7690 including 578 FFs, almost the same fault coverage is achieved with fewer scan FFs than a conventional method based on gate level testability analysis.

• 社団法人電子情報通信学会の論文
• 1998-12-25

著者

• Noda Hiroaki

  The Precision Technology Development Center Sharp Corporation

• TAKAHASHI Mizuki

  the Design Technology Development Center, IC Group, SHARP Corporation

• SAKURAI Ryoji

  the Design Technology Development Center, IC Group, SHARP Corporation

• KAMBE Takshi

  the Design Technology Development Center, IC Group, SHARP Corporation

• Takahashi Mizuki

  The Design Technology Development Center Ic Group Sharp Corporation : The Graduate School Of Enginee

• Kambe Takshi

  The Design Technology Development Center Ic Group Sharp Corporation

• Sakurai Ryoji

  The Design Technology Development Center Ic Group Sharp Corporation

関連論文

• Register-Transfer Level Testability Analysis and Its Application to Design for Testability (Special Section on VLSI Design and CAD Algorithms)
• Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes (Special Section on VLSI Design and CAD Algorithms)

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