Instruction Sequence Based Synthesis for Application Specific Micro-Architecture (Special Section of Papers Selected from ITC-CSCC'96)

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概要

• 論文の詳細を見る

• In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.

• 社団法人電子情報通信学会の論文
• 1997-06-25

著者

• Kunieda Hiroaki

  Faculty Of Engineering Tokyo Institute Of Technology

• Jang K‐s

  Faculty Of Engineering Tokyo Institute Of Technology

• JANG Kyung-Sik

  Faculty of Engineering, Tokyo Institute of Technology

• ISSHIKI Tsuyoshi

  Faculty of Engineering, Tokyo Institute of Technology

• Isshiki Tsuyoshi

  Faculty Of Engineering Tokyo Institute Of Technology

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