Memory Sharing Processor Array (MSRA) Architecture (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome over-lapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.

• 社団法人電子情報通信学会の論文
• 1996-12-25

著者

• Kunieda Hiroaki

  Faculty Of Engineering Tokyo Institute Of Technology

• Li Dongju

  Faculty Of Engineering Tokyo Institute Of Technology

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