A High Speed, Switched-Capacitor Analog-to-Digital Converter Using Unity-Gain Buffers

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概要

• 論文の詳細を見る

• A cyclic analog-to-digital (A / D) converter is developed which accomplishes an n-b conversion in n / 2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A / D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-μm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A / D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A / D conversion.

• 社団法人電子情報通信学会の論文
• 1993-06-25

著者

• Watanabe Kenzo

  The Research Institute Of Electronics Shizuoka University

• Watanabe Kenzo

  The Reesearch Institute Of Electronics Shizuoka University

• OGAWA Satomi

  the Research Institute of Electronics, Shizuoka University

• Ogawa Satomi

  The Research Institute Of Electronics Shizuoka University

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