Test Generation for Sequential Circuits Using Partitioned Image Computation (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first / depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100 fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

• 社団法人電子情報通信学会の論文
• 1993-10-25

著者

• Ishiura Nagisa

  The Faculty Of Engineering Osaka University

• Maeda Hironori

  The Faculty Of Engineering Osaka University

• Shirakawa Isao

  the Faculty of Engineering, Osaka University

• Choi Hoyong

  the Faculty of Engineering, Osaka University

• Kohara Takashi

  the Faculty of Engineering, Osaka University

• Motohara Akira

  the Semiconductor Research Center, Matsusita Electric Industrial Co., Ltd.,

• Choi Hoyong

  The Faculty Of Engineering Osaka University

• Kohara Takashi

  The Faculty Of Engineering Osaka University

• Motohara Akira

  The Semiconductor Research Center Matsusita Electric Industrial Co. Ltd.

• Shirakawa Isao

  The Faculty Of Engineering Osaka University

関連論文

• A Recycling Scheme for Layout Patterns Used in an Old Fabrication Technology (Special Section on JTC-CSCC '92)
• Test Generation for Sequential Circuits Using Partitioned Image Computation (Special Section on VLSI Design and CAD Algorithms)
• A Distributed Routing System for Multilayer SOG (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

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