A High Resolution, Wide Range Digital Impedance Controller(<Special Section>Papers Selected from AP-ASIC 2004)

概要

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This paper describes a digital impedance controller (DIC) [1] for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23Ω to 140Ω with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is 2.26% with RQ ranging from 23Ω to 53Ω, the same range covered by conventional scheme. The high resolution and wide range impedance control is implemented by using automatic gate voltage optimization. The amount of jitter caused by quantization error is 6.9 ps while 13.8 ps in conventional scheme. The data input valid window is 623 ps at 0.75±200 mV and maximum eye open is 641 mV meaning about 10% improvement at 1.5 Gbps/pin DDR3 SRAM interface.
2005-08-01