Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages(Passive Circuits, <Special Section>Recent Technologies of Microwave and Millimeter-Wave Devices Focusing on Miniaturization and Advancement in Performa
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概要
- 論文の詳細を見る
In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.
- 社団法人電子情報通信学会の論文
- 2005-07-01
著者
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NISHINO Tamotsu
Information Technology R & D Center, Mitsubishi Electric Corporation
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Yuasa Takeshi
Information Technology R&d Center Mitsubishi Electric Corporation
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Ohhashi Hideyuki
Information Technology R&d Center Mitsubishi Electric Corporation
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Nishino Tamotsu
Mitsubishi Electric Corp. Kamakura‐shi Jpn
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