Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems(Electronic Circuits)

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概要

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• This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is ±1.5×T_<CLK>. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

• 一般社団法人電子情報通信学会の論文
• 2005-05-01

著者

• Baek Kwang

  High-speed Mixed-signal Department Rockwell Scientific Company

関連論文

• High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers(Circuit Theory)
• Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems(Electronic Circuits)

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