High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers(Circuit Theory)

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概要

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• This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.

• 社団法人電子情報通信学会の論文
• 2005-05-01

著者

• Baek Kwang

  High-speed Mixed-signal Department Rockwell Scientific Company

• Baek Kwang‐hyun

  High-speed Mixed-signal Department Rockwell Scientific Company

• MERLO Edward

  High-Speed Mixed-Signal Department, Rockwell Scientific Company

• Merlo Edward

  High-speed Mixed-signal Department Rockwell Scientific Company

関連論文

• High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers(Circuit Theory)
• Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems(Electronic Circuits)

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