A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector(<Special Section>Analog Circuit and Device Technologies)

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概要

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• An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operationis achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

• 2004-06-01

著者

• Kunieda Hiroaki

  Tokyo Institute Of Technology

• Idei Gijun

  Tokyo Institute Of Technology

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