A Design for Testability Technique for Low Power Delay Fault Testing(<Special Section>Low-Power System LSI, IP and Related Technologies)

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概要

• 論文の詳細を見る

• This paper presents a Quiet-Noisy scan technique for low power delay fault testing. The novel scan cell design provides both the quiet and noisy scan modes. The toggling of scan cell outputs is suppressed in the quiet scan mode so the power is saved. Two-pattern tests are applied in the noisy scan mode so the delay fault testing is possible. The experimental data shows that the Quiet-Noisy scan technique effectively reduces the test power to 56% of that of the regular scan. The transition fault coverage is improved by 19.7% compared to an existing toggle suppression low power technique. The presented technique requires very minimal changes in the existing MUX-scan Design For Testability (DFT) methodology and needs virtually no computation. The penalties are area overhead, speed degradation, and one extra control in test mode.

• 社団法人電子情報通信学会の論文
• 2004-04-01

著者

• Li James

  Electrical Engineering Department

• Li James

  Electrical Engineering Department/giee National Taiwan University(ntu)

関連論文

• Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns(VLSI Design Technology and CAD)
• A Design for Testability Technique for Low Power Delay Fault Testing(Low-Power System LSI, IP and Related Technologies)

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