Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• A diagnosis technique is presented to locate at least one fault in a scan chain with multiple timing faults. This diagnosis technique applies Single Excitation (SE) patterns of which only one bit can be flipped even in the presence of multiple faults. By applying the SE patterns, the problem of simulations with unknown values is eliminated. The diagnosis result is therefore deterministic, not probabilistic. Experiments on the IS-CAS benchmark circuits show that the average diagnosis resolution is less than ten scan cells.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Li James

  Electrical Engineering Department

関連論文

• Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns(VLSI Design Technology and CAD)
• A Design for Testability Technique for Low Power Delay Fault Testing(Low-Power System LSI, IP and Related Technologies)

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