A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit(<Special Section>Low-Power System LSI, IP and Related Technologies)

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概要

• 論文の詳細を見る

• We present a single-chip MPEG-4 audiovisual LSI in a 0.13 μm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5GOPS post filtering unit. It consumes 160mW at 125MHz and dissipates 80nA in the standby mode. The chip is the world first LSI handling MPEG-4 GIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.

• 社団法人電子情報通信学会の論文
• 2004-04-01

著者

• Ueda Yasuyuki

  Toshiba Corp.

• Fujita Tetsuya

  Toshiba Corp.

• Tsuboi Yoshiro

  Toshiba Corp.

• FUJIYOSHI Toshihide

  Toshiba Corporation

• TAKAHASHI Masafumi

  Toshiba Corporation

• ARAKIDA Hideho

  Toshiba Corp.

• NISHIKAWA Tsuyoshi

  Toshiba Corp.

• YAMAMOTO Hideaki

  Toshiba Corp.

• KITASHO Yoshiyuki

  Toshiba Corp.

• Fujiyoshi Toshihide

  Toshiba Corp.

• Takahashi Masafumi

  Toshiba Corp.

関連論文

• Module-Wise Dynamic Voltage and Frequency Scaling for a 90nm H.264/MPEG-4 Codec LSI (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• Monte Carlo Analysis of Velocity Overshoot Effects in Bipolar Devices with and without an i-Layer (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
• Mechanical Stress Analysis of Trench Isolation Using a Two-Dimensional Simulation (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD93))
• A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit(Low-Power System LSI, IP and Related Technologies)

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