A 30V High Voltage NMOS Structure Design in Standard 5V CMOS Processes(Semiconductor Materials and Devices)

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概要

• 論文の詳細を見る

• This paper describes the robust design of the 30V high voltage NMOS (HVNMOS) structure implemented in a 0.6μm 5V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively By varying the six spacing parameters : the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11V, and the breakdown voltage of the HVNMOS is increased to over 30V. With the optimized layout parameters of the HVNMOS, it can be increased to 38V.

• 一般社団法人電子情報通信学会の論文
• 2003-11-01

著者

• Lin T‐c

  Integrated Circuit And Systems Laboratory Department Of Electronics Engineering National Chiao-tung

• Wu Jiin-chuan

  Integrated Circuit And Systems Laboratory Department Of Electronics Engineering National Chiao-tung

• Wu Jiin-chuan

  Integrated Circuit And Systems Laboratory Department Of Electronics Engineerin National Chiao-tung U

• Lin Tzu-chao

  Integrated Circuit And Systems Laboratory Department Of Electronics Engineering National Chiao-tung

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