A 30 V High Voltage NMOS Structure Design in Standard 5 V CMOS Processes
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概要
- 論文の詳細を見る
- 2003-11-01
著者
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Wu Jiin-chuan
Integrated Circuit And Systems Laboratory Department Of Electronics Engineerin National Chiao-tung U
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Wu Jiin-chuan
Integrated Circuit And Systems Laboratory Department Of Electronics Engineering National Chiao-tung
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Lin Tzu-chao
Integrated Circuit And Systems Laboratory Department Of Electronics Engineering National Chiao-tung
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